Design and analysis of signal conditioning circuit for capacitive sensor interfacing

This paper presents design and analysis of a capacitive sensor interfacing circuit, which detects the physical signal as a change in capacitance and provides voltage output. Theoretical analysis of synchronous chopper modulation and demodulation is carried out and it is shown that how this technique is utilized to remove the low frequency noise and offset voltage introduced by the operational amplifier. The signal conditioning circuit comprises of a buffer, amplifier, demodulator and low pass filter. Detailed analysis of the circuit, considering sinusoidal variation of change in capacitance is presented. Two demodulator circuit topologies are analysed and their merits and demerits are highlighted. The complete circuit is designed and simulated in UMC 180 nm CMOS process technology and the simulation results are presented.