Low power high speed 1-bit full adder circuit design at 45nm CMOS technology | IEEE Conference Publication | IEEE Xplore

Low power high speed 1-bit full adder circuit design at 45nm CMOS technology


Abstract:

One bit full adder cell is one of the most frequently used digital circuit component in arithmetic logic unit (ALU) and it is the essential functional unit of all computa...Show More

Abstract:

One bit full adder cell is one of the most frequently used digital circuit component in arithmetic logic unit (ALU) and it is the essential functional unit of all computational circuit. Till now lots of improvement has been done in this area to refine the architecture and performance of full adder circuit design. In this paper two designs of novel 1-bit full adder cell at 45nm CMOS technology is implemented by using ten transistors (10-T) along with the three existing 1-bit full adder cell. Later the complete comparison and verification is performed with the different existing and proposed adder cells on different supply voltages at 100MHz operating frequency. From the simulation results by performing the comparison among proposed adder cells and existing adder cells it is found that the proposed adder cells are better than the existing adder cells in terms of power consumption, delay and power delay product (PDP). From the simulation result it is observed that the first proposed adder circuit using XOR module has achieved maximum saving of power 91.65%, saving of delay 59.37% and saving of overall PDP of 91.64% when compared to existing Static Energy Recovery Full (SERF) full adder and Gate Diffusion Input (GDI) full adder circuit respectively. When second proposed adder circuit using XOR module is compared with existing SERF and GDI adder circuit maximum saving of power 93.04%, saving of delay 76.76% and saving of overall PDP of 96.01% is achieved. All above statistical analysis is given by performing the comparison between existing and proposed adder circuits which have same number of transistors count (10-T) in designing at supply voltage 1 volt.
Date of Conference: 27-29 October 2017
Date Added to IEEE Xplore: 11 June 2018
ISBN Information:
Conference Location: Bhopal, India

I. Introduction

Demand for usage of battery based portable electronic system is increasing day by day, as the devices are portable they need battery for driving them. So power consumption and speed becomes the main concern in designing of devices such as laptops, tablets, mobile phones, notebooks, and many other personal communication devices. The power consumption plays vital role in VLSI technology. More power consumption leads to more heating which results in decreasing battery life and also needs cooling fan to cool the circuitry. Therefore power consumption affects the battery life and the cost of the whole system. Mostly all digital communication devices and the devices about which we have discussed above are used in the applications like digital signal processing, image and video processing, microcontrollers and these applications uses various arithmetic and logic operations to perform addition, subtraction, multiplication etc. All these operations like addition subtraction and multiplication could be performed internally with the help of adder cells only. Since one bit adder circuit (cell) plays most important role in designing these digital communication devices. Frequently all digital communication devices have multiple numbers of 1-bit full adder cells integrated within it to perform one or many bits addition operation, this is the reason adder cell plays an important role in determining the performance of the whole system.

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References

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