A 32 Gb/s ADC-based PAM-4 receiver with 2-bit/stage SAR ADC and partially-unrolled DFE | IEEE Conference Publication | IEEE Xplore

A 32 Gb/s ADC-based PAM-4 receiver with 2-bit/stage SAR ADC and partially-unrolled DFE


Abstract:

A PAM-4 ADC-based receiver employs a 32-way time-interleaved 6-bit 2-bit/stage loop-unrolled SAR ADC with a single capacitive reference DAC. Digital equalization complexi...Show More

Abstract:

A PAM-4 ADC-based receiver employs a 32-way time-interleaved 6-bit 2-bit/stage loop-unrolled SAR ADC with a single capacitive reference DAC. Digital equalization complexity is reduced with a new PAM-4 DFE architecture that has a gate count comparable to an NRZ DFE, while simultaneously halving the critical path delay. A 3-tap FFE is embedded in the ADC using an additional non-binary DAC to improve the coverage of the 6-bit FFE coefficient space. This 3-tap embedded FFE and CTLE front-end partial equalization allows placement of the CDR's Mueller-Muller phase detector directly at the ADC output to avoid excessive loop delay. Fabricated in GP 65nm CMOS, the 32Gb/s receiver operates at a BER <; 10-11 with a 27 dB loss channel and <; 10-9 with a 30 dB loss channel without utilizing any transmit equalization. The complete ADC-based receiver achieves a power efficiency of 8.25pJ/bit, including all the front-end, ADC, and DSP power.
Date of Conference: 08-11 April 2018
Date Added to IEEE Xplore: 10 May 2018
ISBN Information:
Electronic ISSN: 2152-3630
Conference Location: San Diego, CA, USA
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