Abstract:
In this paper, a new envelope detector design in a 40nm CMOS technology is presented. The design employs quadrature signal generation and 2nd harmonic cancellation to red...Show MoreMetadata
Abstract:
In this paper, a new envelope detector design in a 40nm CMOS technology is presented. The design employs quadrature signal generation and 2nd harmonic cancellation to reduce output ripple while achieving high detection speed at the same time. The envelope detector operates from 500MHz to 6GHz with a detection speed of 250 MHz. It achieves less than 2% ripple, 0.64 ns delay and consumes 76.9 uW. With the achieved results, it is suitable for use in a nonlinear interference suppression receiver, enabling more than 25 dB of suppression.
Date of Conference: 27-30 May 2018
Date Added to IEEE Xplore: 04 May 2018
ISBN Information:
Electronic ISSN: 2379-447X