Abstract:
A heuristic is presented to efficiently synthesize approximate adder trees on Altera and Xilinx FPGAs using their carry chains. The mapper constructs approximate adder tr...Show MoreMetadata
Abstract:
A heuristic is presented to efficiently synthesize approximate adder trees on Altera and Xilinx FPGAs using their carry chains. The mapper constructs approximate adder trees using an approximate quaternary adder as the fundamental building block. The approximate adder trees are smaller than exact adder trees, allowing more operators to fit into a fixed-area device, trading off arithmetic accuracy for higher throughput.
Date of Conference: 19-23 March 2018
Date Added to IEEE Xplore: 23 April 2018
ISBN Information:
Electronic ISSN: 1558-1101
Keywords assist with retrieval of results and provide a means to discovering other relevant content. Learn more.
- IEEE Keywords
- Index Terms
- Carry Chain ,
- Throughput ,
- Fundamental Building Block ,
- Deep Learning ,
- Savings ,
- Deep Learning Models ,
- Error Analysis ,
- Partial Products ,
- Mapping Algorithm ,
- Compressor ,
- Tree Height ,
- Arithmetic Operations ,
- Compression Ratio ,
- Input Combinations ,
- Least Significant Bit ,
- Critical Path ,
- Independent Input ,
- Programmable Logic ,
- Bit-width ,
- Input Bits ,
- Pivotal Position ,
- OR Gate ,
- Approximation Operators
- Author Keywords
Contents Keywords assist with retrieval of results and provide a means to discovering other relevant content. Learn more.
- IEEE Keywords
- Index Terms
- Carry Chain ,
- Throughput ,
- Fundamental Building Block ,
- Deep Learning ,
- Savings ,
- Deep Learning Models ,
- Error Analysis ,
- Partial Products ,
- Mapping Algorithm ,
- Compressor ,
- Tree Height ,
- Arithmetic Operations ,
- Compression Ratio ,
- Input Combinations ,
- Least Significant Bit ,
- Critical Path ,
- Independent Input ,
- Programmable Logic ,
- Bit-width ,
- Input Bits ,
- Pivotal Position ,
- OR Gate ,
- Approximation Operators
- Author Keywords
