Abstract:
Multiple-clock-cycle, signal adaptive, and fully pipelined hardware design of the optimal (Wiener) space/spatial-frequency (S/SF) filter is developed in this paper. All i...Show MoreMetadata
Abstract:
Multiple-clock-cycle, signal adaptive, and fully pipelined hardware design of the optimal (Wiener) space/spatial-frequency (S/SF) filter is developed in this paper. All implementation and verification details, as well as the extensive comparative analysis, are provided. The developed solution optimizes critical design performances related to the hardware complexity, in line with multiple-clock-cycle nature. Variable (signal adaptive) number of clock cycles, taken within the execution in different S/SF points, provides this solution to retain the optimized time requirements, as well as high resolution, selectivity, and estimation quality of the corresponding recently proposed signal adaptive filtering solution. However, as the major contribution, the fully pipelined implementation enables the developed design to additionally improve the time required for execution. The achieved improvement corresponds to a clock cycle per each S/SF point performed within the estimation that results in the significant comparative improvement in execution time of up to 50% in terms of S/SF points lying outside the local frequency of the estimated 2D frequency-modulated signal. The implementation is tested on a highly nonstationary multicomponent signal and is verified by a field programmable gate array circuit design.
Published in: IEEE Transactions on Circuits and Systems I: Regular Papers ( Volume: 65, Issue: 10, October 2018)