A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems

An ultra-low energy KHz timer/oscillator circuit suitable for heavily duty cycled systems is presented. The proposed oscillator design utilizes a 3-stage ring topology made of CMOS Schmitt trigger delay cells biased with sub-nA currents. To extract a maximum delay per stage, high and low threshold voltages of the delay cells are set at supply and ground potentials, respectively. An ultra low power non-overlap buffer circuit that consumes less than 500 pA current and provides faster transition times of <10ns is designed to minimize the short circuit current in the digital load circuits. The proposed oscillator circuit is fabricated in a 130 nm CMOS process and occupies an area of 0.027 mm
²
. The oscillator circuit consume a total current of 2.18nA from 1V supply, for a 1.87 KHz frequency of oscillation (1.16pJ/cycle). The proposed design operates across a wide supply voltage range of 1.0 V to 3.3 V, and a temperature range of -40°C to 125°C. Measured oscillator performance in this wide operating range is presented in detail.