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A cost and resource efficient telemetry host station design using FPGA | IEEE Conference Publication | IEEE Xplore

A cost and resource efficient telemetry host station design using FPGA


Abstract:

Telemetry is used to acquire data from sensors in a remote location and then transmit to a place (host station) where it can be analyzed. Telemetry systems are used to mo...Show More

Abstract:

Telemetry is used to acquire data from sensors in a remote location and then transmit to a place (host station) where it can be analyzed. Telemetry systems are used to monitor performance parameters of moving vehicles such as cars, aircraft and space shuttles; as well as static objects such as power grids. Telemetry systems use specialized communication modules and data acquisition devices at remote and host stations. Remote station monitors and transmits desired telemetry information. To improve bandwidth efficiency, data from various sources is concatenated to form PCM stream which is transmitted using wired or wireless communication system. A host station for wireless telemetry reception typically consists of a receiver system, a bit synchronizer, a PCM decoder along with data visualizer and data logger. Bit synchronizer receives data from receiver in the form of analog signals, samples it and converts the noisy data into clean data along with generation of a synchronous clock for use in host station. The binary data and clock are provided to a PCM Decoder which decodes the IRIG-106 frame and transmits decoded data using Ethernet to a data visualization system. It also provides the received PCM stream to a data logger. Data logger dumps the acquired PCM stream in an SD card operating at high speed. Design of bit synchronizer involves different challenges like managing the resources of FPGA in an efficient manner. This enables to develop cost effective solutions for telemetry host station especially where multiple host stations may be involved. To verify the design, a host station is set up using Xilinx Spartan 3E, in accordance with IRIG-106 frame standard. The implementation of bit synchronizer uses minimum resources as none of the data is stored in the FPGA, while data and clock are provided in real-time. The decoder complies with the maximum possible frame structure of IRIG-106 standard. In data logger, FAT32 File System is implemented which makes it suitable ...
Date of Conference: 09-13 January 2018
Date Added to IEEE Xplore: 12 March 2018
ISBN Information:
Electronic ISSN: 2151-1411
Conference Location: Islamabad, Pakistan

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