A practical yield prediction approach using inline defect metrology data for system-on-chip integrated circuits

Integrated circuit (IC) yield prediction which focuses on modelling the IC yield characteristics using manufacturing data is an extremely critical task to pursue, this is because it directly impacts the decision making process to improve manufacturing quality, reliability and reduce cost. In this work, we propose a practical yield prediction approach for system-on-chip (SoC) ICs. To achieve finer granularity in modelling and optimization, and better generality across different SoCs, different functional blocks in the SoC are modelled individually. Partial Least Squares (PLS) and Support Vector Regression (SVR) algorithm are used to build yield models, and the prediction results from both algorithms are analyzed and compared. It is shown that SVR has slightly better prediction performance than PLS. Comparison is also done among different functional blocks as well as different wafer radial regions. Static random access memory (SRAM) block and wafer center appear to have better yield predictability from inline defect data among their peers, which suggests inline monitoring scheme may need to be further optimized to capture potential yield impact to other types of SoC functional blocks or wafer edge region.

I. Introduction

The integrated circuit (IC) manufacturing industry has developed extremely rapidly to follow Moore's Law, when the IC process technology comes to the nanometer regime, the complexity and cost of the fabrication process rises dramatically. A wafer in the production cycle will go through hundreds of different process operations taking several months to finish. During this time, typically very little information of the final product quality is collected, resulting in high level of uncertainty of die yield which directly affects the cost and profit of the enterprise.