Towards software performance estimation based on register-transfer level descriptions

The concept of hardware-software codesign allows to cope with the increasing complexity of very large scale integration (VLSI) systems. This concept is based on design space exploration (DSE), which means the systematic altering of design parameters (e.g., parallelization, serialisation, implementation of a functionality in software or hardware) to improve the final design. Existing DSE approaches work with high-level descriptions (e.g., SystemC) of the functionality. However, if existing systems (or submodules of those) shall be reused, only a synthesizable register-transfer level (RTL) description of these functionalities is necessarily given. Consequently, the RTL modules cannot be considered during the DSE. We propose an approach to this problem of reasonable practical relevance. To conduct the DSE, we estimate the software execution time of a functionality based on its RTL description. We show in an evaluation that this estimation is possible based on RTL code. In addition, we propose several suggestions to mitigate the problem that the software execution time of a functionality is highly dependent on the input data, which are often unknown at design time.