HV latchup — Power analog ICs co-design with block level verification | IEEE Conference Publication | IEEE Xplore

HV latchup — Power analog ICs co-design with block level verification


Abstract:

Power Analog ICs which contain both high voltage and low voltages cells require a unique approach to achieve latchup robustness. A methodology was developed to allow both...Show More

Abstract:

Power Analog ICs which contain both high voltage and low voltages cells require a unique approach to achieve latchup robustness. A methodology was developed to allow both schematic and layout block level latchup verification automation as applied to HV Latchup in Power Analog ICs design. The methodology enables co-design between schematic design and layout design, improving silicon success as well as shortening the design cycle.
Date of Conference: 10-14 September 2017
Date Added to IEEE Xplore: 19 October 2017
ISBN Information:
Conference Location: Tucson, AZ, USA

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