Abstract:
This paper presents a high-speed VLSI implementation structure for adder. Innovative serial implementations of carry-look-ahead adders ore developed. The critical path in...Show MoreMetadata
Abstract:
This paper presents a high-speed VLSI implementation structure for adder. Innovative serial implementations of carry-look-ahead adders ore developed. The critical path in CLA adders, where the carry is propagated, is implemented using a parallel structure. The supply voltage (V/sub dd/) is 3.9 v which con be lowered to 2.5 v. The adder is in 0.8 /spl mu/m technology. HSPICE simulation shows a total delay of 1.2 ns for 32-bits CLA adder.
Date of Conference: 09-12 May 1999
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-5579-2
Print ISSN: 0840-7789
