Optimizing Memory Access Performance Using Hardware Assisted Virtualization in Retargetable Dynamic Binary Translation

Dynamic Binary Translation is one of the most efficient strategies for the simulation of System-on-Chips, with recent studies showing that a large part of the simulation time is spent in realizing memory accesses. Indeed, the simulation of each load and store instructions requires a software emulation of the hardware Memory Management Unit (MMU). In this work, we propose to realize memory accesses in hardware, taking advantage of the hardware-assisted virtualization capabilities that are now available in modern processors. To do so, we have to setup and maintain shadow page tables, like any regular hypervisor would do, running the entire simulator on a virtual CPU. Now, each load and store instructions can be translated to just a couple of load and store instruction, executing at regular speed, therefore avoiding entirely the overhead of the software emulation of hardware MMU. The goal of this paper is to explain how it can be done. To demonstrate our idea, we have implemented our approach in the QEMU retargetable DBT engine, speeding up the simulation by as much as 40%.

I. Introduction

209.126.136.6 The performance of the simulation of Systems-on-Chips (SoC) is a growing concern as their complexity grows. Nowadays, many SoCs integrate multiple cores and many complex specialized circuit. Moreover, more and more SoCs are designed per year, even if only a small percentage actually reaches the silicon and finally the market. For example, in a decade, Qualcomm released 118 different Snapdragon SoCs and Nvidia commercialized around 33 Tegra SoCs. In this context, relying on the simulation of these SoCs is a fact of life for engineers, using simulation to deploy boot software, device drivers, operating systems and applications, long before the SoC may reach the silicon, if it ever does. But, in order to be useful for software development, simulators need to be fast.