I. Introduction
Due to the demand of the wide bandwidth of analog and RF circuits, low-dropout regulators (LDOs) are expected to provide a high power-supply rejection ratio (PSRR) over a wide frequency range. In general, LDOs can be categorized according to the location of the dominant pole, . First, when is at , as shown in Fig. 1(a), an LDO easily can achieve a high PSRR at high frequencies. However, for this topology, the LDO could become unstable as the load current, , increases, since moves towards the gate-pole of the pass-transistor . Thus, to secure the stability of the LDO even when is large, the size of the load capacitor, , must be very large. Practically, the size of could increase to several , which makes the use of a high-cost external capacitor inevitable. To reduce the size of to an integration-available level, [1] presented an LDO that used a wideband error-amplifier to push far from . However, the reduced gain of the error-amplifier degraded the PSRR at frequencies less than the unity-gain frequency, . On the other hand, when is dominant , as shown in Fig. 1(b), an LDO does not require a large , but must have a PSRR-hump in a high frequency range, as shown in Fig. 1(b). To suppress this PSRR-hump, [2]–[5] presented a supply-ripple cancellation (SRC) technique, where the ripples copied from the supply, , were injected to [2]–[4] or the body gate of [5]. However, based on a feedforward method, in which the magnitude of the injecting ripples was predefined, the PSRRs of the LDOs in [2]–[3], [5] were susceptible to the variation of or the dropout voltage, . The SRC in [4] used a technique to mitigate the sensitivity of a PSRR, but it had a limitation to improve a PSRR, since it could not cancel ripples through the output impedance of . (This is one of major coupling paths in a deep sub-micron technology.)
LDOs with the dominant pole (a) at the output, i.e., ; (b) at the gate, i.e., , having a supply-ripple cancellation (SRC) technique