Design of tunable digital delay cells

This work discusses design considerations for implementing widely tunable delay cells with good matching properties, low jitter, and robust communication to adjacent circuits. Previously unreported effects that result in signal-dependent delay are discussed and eliminated. A 1.2 V 65 nm CMOS prototype achieves a tunability range from 5 ns to 10 μs, with a matching standard deviation of 2.3% and a jitter standard deviation of 0.065%.

I. Introduction

Tunable digital delay elements are widely used in integrated circuits; e.g. in DLLs and PLLs to generate accurate clocks [1], in delay-line-based time-to-digital converters [2], in asynchronous systems processing bundled data to ensure correct system timing [3], and in continuous-time signal processors (CT-DSP) to set the frequency response [4]. Delay cells are expected to have some or all of following attributes: ♦

Wide tuning range;

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Good matching between identically laid out cells;

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Low jitter;

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Signal-independent delay;

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Robust communication, in order to guarantee correct propagation of every input event.