Abstract:
We propose a highly scalable packet-switching architecture that suits for demanding Data Center Networks (DCNs). The design falls into the category of buffered multistage...Show MoreMetadata
Abstract:
We propose a highly scalable packet-switching architecture that suits for demanding Data Center Networks (DCNs). The design falls into the category of buffered multistage switches. It affiliates the three-stage Clos-network and the Networks-on-Chip (NoC) paradigm. We also suggest a congestion-aware routing algorithm that shares the traffic load among the switch's central modules via interleaved connecting links. Unlike conventional switches, the current proposal provides better path diversity, simple scheduling, speedup and robustness to load variation. Simulation results show that the switch scales well with the port-count and traffic fluctuation and that it outperforms different switches under many traffic patterns.
Published in: 2017 IEEE 18th International Conference on High Performance Switching and Routing (HPSR)
Date of Conference: 18-21 June 2017
Date Added to IEEE Xplore: 07 July 2017
ISBN Information:
Electronic ISSN: 2325-5609