A statistical modeling methodology of RTN gate size dependency based on skewed ring oscillators

This paper proposes a statistical modeling methodology of RTN (Random Telegraph Noise) gate size dependency utilizing skewed ring oscillator (RO) structures. An iterative characterization flow is developed to estimate RTN induced threshold distribution of each gate sizes of pMOSFET and nMOSFET independently. The skewed RO based test structure was fabricated in a 65 nm SOTB (Silicon On Thin Body) process. It is observed that Lognormal distribution represents RTN induced delay distribution well. RTN model of gate size dependency is then developed and validated using the measured data. Model based delay distribution estimation and measurement match well. The proposed extraction methodology is thus suitable for estimating RTN of transistors with arbitrary gate size. The model helps reliability and worst case analysis of digital circuits where transistors of various gate sizes are used.