Abstract:
This paper follows recent research on insufficient synthesis performance for XOR-intensive circuits, and introduces a novel logic representation with a native support of ...Show MoreMetadata
Abstract:
This paper follows recent research on insufficient synthesis performance for XOR-intensive circuits, and introduces a novel logic representation with a native support of XOR gates, the XOR-AND-Inverter Graphs (XAIGs). A rewriting algorithm over XAIG has been implemented in the logic synthesis and optimization package ABC, as the first step towards a complete synthesis process. The results show that XAIG based rewriting can help to discover XORs and improves the area of a mapped network in some cases.
Published in: 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
Date of Conference: 19-21 April 2017
Date Added to IEEE Xplore: 29 May 2017
ISBN Information:
Electronic ISSN: 2473-2117
Faculty of Information Technology, Czech Technical University in Prague, Prague, Czech Republic
Faculty of Information Technology, Czech Technical University in Prague, Prague, Czech Republic
Faculty of Information Technology, Czech Technical University in Prague, Prague, Czech Republic
Faculty of Information Technology, Czech Technical University in Prague, Prague, Czech Republic
Faculty of Information Technology, Czech Technical University in Prague, Prague, Czech Republic
Faculty of Information Technology, Czech Technical University in Prague, Prague, Czech Republic