Formal Verification of Power Management Logic with Mixed-Signal Domains

System on Chip (SoC) designs today have a large number of power domains regulated by complex on-chip power management logic. The power management logic is primarily digital in nature, but it relies on analog components such as Low Dropout Regulators (LDO) and Phase-Locked Loops (PLL) for delivery of regulated voltages and clock frequencies. In low power designs, such analog components may also be powered down at times, and hence power domains are defined around modules containing these components. The digital brain of the power management logic must correctly consider the latencies of the analog components in the power management fabric while switching the power domains driven by these components. This is a task which has become extremely complex by virtue of the multitude of LDOs and PLLs in a modern integrated circuit, and the numerous domains that they drive. This paper presents, for the first time, a formal verification methodology for automatically generating the necessary assertions from an extended syntax of the Unified Power Format (UPF) and proving them on the power management logic using available industrial formal verification tools.

I. Introduction

Bugs in the power management logic often escape pre-silicon verification because power aware simulation is expensive. These bugs have complex manifestations in post-silicon, typically in the form of data corruption. It is usually hard to verify the power management logic in isolation, that is, without tying it up with rest of the circuit which it drives, unless we are given a (formal) specification that separates incorrect behaviors of the power management logic from the correct ones. On the other hand, power domain transitions follow well defined sequences consisting of routine steps like isolation, retention and power gating [1] and such sequences can be captured through assertions expressed in languages like SystemVerilog Assertions (SVA) or Property Specification Language (PSL). There are commercial offerings [2], [3] today that can read the definitions of power domains in language standards such as Unified Power Format (UPF) [4] and Common Power Format (CPF) [5] and extract the relevant sequencing assertions [6]. These assertions, as well as others gleaned from the architectural specification of the power intent can be proven on the power management logic using formal verification techniques, as reported in [7], [8]. Verification of the power management logic against a formal specification of the power intent is a less expensive and more comprehensive option for pre-silicon validation of power management logic, as compared to power-aware simulation.