Contents I. Introduction
Flyback and forward converters are traditional topologies commonly used for low-to-medium power isolated applications [1]–[3]. The efficiency, performance, power density, and form factor of these topologies highly depend on the characteristics of the transformer, which is a key part of these converters. Fig. 1(a) shows the topology of a flyback converter and provides a list of important challenges in designing high-efficiency high-power-density flyback converters. The transformer leakage inductance significantly affects the performance of flyback and forward power converters, especially for the flyback topology. Large leakage inductances that are present in the traditional wire-wound transformers cause large voltage spikes on the switch, leading to the selection of switches with higher rated voltage. Beside, large voltage spike creates large , which creates common-mode (CM) noise in the switch parasitic capacitance [4] and transformer interwinding capacitance. The transformer form factor also significantly affects the overall height and size of the converter, as usually it is the tallest and bulkiest part of the circuit. Due to their high height, traditional cores cannot be used in certain low-profile applications like flat TVs or portable devices. Higher height also is a disadvantage from the heat transfer point of view, as it leads to high thermal resistance. Fig. 1(b) summarizes the aforementioned drawbacks of wire-wound transformers. Some of these problems can be resolved using planar transformers (PTs), which are well suited to flat implement slim-profile power converters. They provide extremely low leakage inductances that cannot be attained using traditional wire-wound transformers and elaborated interleaved structures can be implemented easily in PTs in such a way as to minimize the ac resistance [5], [6]. PTs also offer exceptionally low thermal resistance (due to their higher surface to height ratio), repeatability, and manufacturing simplicity [7]–[11]. Despite these advantages, PTs have extremely high interwinding parasitic capacitance, due to the proximity of the layers and their significant overlap, and this generates large levels of CM noise leading to serious EMI problems [12]– [20]. In general, CM noise is created by the displacement current that flows from the voltage pulsating nodes in the circuit to the protective earth (PE) through the parasitic capacitance [20]. Fig. 1(a) shows how CM noise currents are generated in the parasitic capacitances and circulate in the circuit. According to this figure, transformer parasitic capacitances play a major role in CM noise generation. These parasitic capacitances not only generate CM noise, but also provide a path for secondary-side parasitic capacitances and lead to the generation of CM noise currents in these parasitic capacitances. While interleaved structures that have many intersections between primary and secondary windings can significantly reduce ac resistance and leakage inductance and enhance the efficiency of the transformer, they also lead to very large parasitic capacitance, which increases the level of CM noise generated. Higher levels of CM noise require more attenuation to comply with standards and regulations, and this requires the use of larger CM choke filters at the input of the converter. To date, no method of reducing winding capacitances can reduce ac resistance and leakage inductance [10]. This problem is considered thoroughly in this paper, and a solution is proposed to attain very low CM noise and high efficiency simultaneously for PTs. Fig. 1(c) presents the advantages of the proposed PTs in this paper. The proposed PTs not only have very low ac resistance and leakage inductance (as a result of highly interleaved structures), but also have near-zero CM noise emission. Indeed, while the proposed PTs have a very large interwinding capacitance, they generate close to zero CM noise due to the paired layers concept, which significantly reduces the size of the required CM choke filters.
