3D-SoC integration utilizing high accuracy wafer level bonding

This paper describes ultra-fine pitch 3D integration development using wafer level Cu/insulator hybrid bonding approach on 300mm substrate. Via-middle process with TSV dimension of 5×50μm is utilized to demonstrate and characterize vertical interconnects formed via face-to-face wafer-to-wafer (W2W) bonding. Key process steps are introduced with specific requirements and challenges. A non-SiO₂ insulator is studied and chosen to enable a high mechanical bond strength with a low temperature anneal (≤250 °C). High alignment accuracy (<; 400nm) is achieved with an advanced bonding system, which allows comprehensive characterizations of interconnect pitch scaling through various test structures. Finally, a high repeatability of the electrical performance of 3.6 μm pitch bonded structures is demonstrated statistically across numerous wafer pairs thanks to the precise Cu-Cu contacts established during bonding.