Bank-Group Level Parallelism

DDR4 SDRAM introduced a new hierarchy in DRAM organization: bank-group (BG). The main purpose of BG is to increase I/O bandwidth without growing DRAM-internal bus-width. We, however, found that other benefits can be derived from the new hierarchy. To achieve the benefits, we propose a new DRAM architecture using the BG-hierarchy, leading to a creation of BG-Level Parallelism (BGLP). By exploiting BGLP, the overall parallelism grows in DRAM operations. We also argue that BGLP is a feasible solution in the cost-sensitive DRAM industry because the additional cost is negligible and only cost-insensitive area needs to be modified.

1 Introduction

DDR4 SDRAM has become a dominant memory device for main-memory systems in computers. DDR4 provides much better infrastructure compared to DDR3: more capacity, higher I/O-bandwidth, and more bank-level parallelism. To accomplish that, DDR4 adopted several new design techniques. One of the techniques is building a new hierarchy in DRAM-organization, namely Bank-Group (BG) [3], [20]. This paper concerns the BG-hierarchy.