High-Level Designs of Complex FIR Filters on FPGAs for the SKA

High-end FPGAs are widely adopted as hardware accelerators, due to their power efficiency, flexibility, and high-performance computing ability. They are, therefore, extremely useful devices for a project with challenges and constraints such as the Square Kilometre Array (SKA). However, the traditional design methods require expert hardware knowledge and long development times for each of the SKA's target applications, making it difficult to make the most out of an array of FPGAs as a shared resource. High-level development approaches are positioned to overcome this issue. In this paper, we investigate the development efficiency and achievable performance of two popular high-level methods, Maxeler's MaxCompiler and OpenCL. They are evaluated by implementing a lengthy FIR filter with complex single precision floating-point (SPF) numbers, both in time and frequency domains (TDFIR and FDFIR, respectively). Our results show that high performance can be achieved with low development effort using such high-level methods, where OpenCL outperforms the MaxCompiler for TDFIR. OpenCL is flexible enough to develop and compare different filter approaches quickly, and as expected FDFIR based implementations clearly outperform TDFIR based ones. To demonstrate OpenCL portability and to compare performance with GPUs, the filters are also evaluated on a GPU platform. The evaluation shows that while the GPU performs better in TDFIR, is is outperformed by the FPGA in FDFIR.