The Potential and the Drawbacks of Underlap Single‐Gate Ultrathin SOI MOSFET

This chapter describes the performance of underlapped single‐gate ultrathin (USU) silicon‐on‐insulator metal oxide semiconductor field‐effect transistors SOI MOSFETs with a low‐k or high‐k gate dielectric from the viewpoint of both digital and analog applications. Increase in underlap length suppresses the threshold voltage variation as well as short‐channel effects. The thickness of the SOI layer also impacts the maximization of drive current (i.e., minimization of intrinsic delay time) directly. As the gate‐underlap region reduces the fringe capacitance of the gate electrode, effective gate capacitance is also reduced, while voltage gain of the device rises. As an apparent rise in cut‐off frequency stems from the reduction of the voltage gain, the advancement of analog performance is inherently limited.Use of a high‐k gate dielectric basically reduces the gate‐induced drain leakage (GIDL) current, while short‐channel effects are degraded. In the case of very high dielectric constant, however, a very high electric‐field region appearing far from the gate edge becomes a new source of high GIDL current. So, optimization of the dielectric constant of the gate insulator is required.