The REPLICA on-chip network

General purpose chip multiprocessors (CMP) are challenging to on-chip intercommunication network designers since one would need low latency, high bandwidth independently of the communication patterns, support for cost-efficient synchronization, and low energy consumption to support arbitrary applications. Currently popular ring-based networks provide straight-forward design, far superior performance than bus-based alternatives and extensibility over crossbars. As the number of processors cores increases, however, the effective bandwidth between most parts of a ring remains constant implying higher capacity solutions are needed to support scaled-up CMPs. In this paper we describe the on-chip network of our REPLICA CMP. It is based on an acyclic bandwidth-scaled multi-mesh topology and uses routing with elastic synchronization mechanism. To avoid congestion and hot spots in shared memory access traffic can be randomized with a programmable hashing function. The performance of the network is evaluated preliminarily on our experimental 4-core and 16-core REPLICA FPGA implementations and REPLICA simulator.