Abstract:
In this paper we review latchup protection verification methods and EDA challenges. We demonstrate complex static and transient latchup scenarios requiring advanced conne...Show MoreMetadata
Abstract:
In this paper we review latchup protection verification methods and EDA challenges. We demonstrate complex static and transient latchup scenarios requiring advanced connectivity analysis. Using various EDA verification flows and tools we study latchup problems associated with grounded n-wells, biased n-wells and parasitic thyristors formed during ESD events.
Date of Conference: 11-16 September 2016
Date Added to IEEE Xplore: 18 October 2016
ISBN Information: