Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching

This brief presents a 7-bit 700-MS/s four-way time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC). A partial V_cm-based switching method is proposed that requires less digital overhead from the SAR controller and achieves better conversion accuracy. Compared with switchback switching, the proposed method can further reduce the common mode variation by 50%. In addition, the impacts of such a reduction on the comparator offset, noise, and input parasitic are theoretically analyzed and verified by simulation. The prototype fabricated in a 65-nm CMOS technology occupies an active area of 0.025 mm². The measurement results at the 700 MS/s sampling rate show that the ADC achieves signal-to-noise-and-distortion ratio of 40 dB at Nyquist input and consumes 2.72 mW from a 1.2 V supply, which results in a Walden FoM of 48 fJ/conversion step.

I. Introduction

High-speed (>500 MS/s sampling rate) and low-to-medium-resolution (5- to 7-bit) ADCs are widely utilized in ultrawide band communication systems [1]. The successive approximation register (SAR) ADC is a power efficient architecture due to its fully dynamic operation and simple structure, as well as its benefits over technology scaling. With the development of modern nanometer CMOS technologies and advanced circuit solutions, the SAR ADC can achieve high speed [1]–[3] and becomes a competitive alternative for such applications.