Identifying systematic spatial failure patterns through wafer clustering

In this paper, we propose a novel methodology for detecting systematic spatial failure patterns at wafer level for yield learning. Our proposed methodology takes the testing results (i.e., pass or fail) of a number of dies over different wafers, cluster all these wafers according to their failures, and eventually identify the underlying spatial failure patterns. Several novel machine learning algorithms, including singular value decomposition, hierarchical clustering, dictionary learning, etc., are developed in order to make the proposed methodology robust to random failures. The efficacy of our proposed approach is demonstrated by an industrial data set.

I. Introduction

The challenges associated with designing and manufacturing of leading edge integrated circuits (IC) have increased with the complexity of chip functionalities. Such complex functionalities have been made possible by the continuous drive towards scaling IC technologies [1]. However, with such scaling, catastrophic defects and process variations stand out among the most important factors limiting the product yield of IC designs [2]–[5].