Contents I. Introduction
Sensitivity to clock jitter is a well known problem with continuous-time modulators (CTDSM). One way to mitigate this is to use a switched capacitor resistor (SCR) feedback DAC [1]. The operation of such a DAC is explained with the aid of Fig. 1(a), which shows the expanded view of the input stage of a typical CTDSM. The input conductance is denoted by . The sampling frequency (period) of the modulator is denoted by . The timing diagram is shown in part (b) of the figure. is a very narrow pulse, whose width ideally tends to zero. The loop filter output is sampled and quantized on the rising edge of , and the quantizer output is assumed to be available immediately. is sampled on the DAC capacitor of value at the end of (Fig. 1(c)). In the next phase , the capacitor discharges into the virtual ground of the opamp through the conductance . The resulting DAC pulse, which has a peak value of , decays exponentially with a time constant . If , the capacitor is completely discharged by the end of , and a charge is transferred into the loop filter. Thanks to the exponentially decaying nature of the DAC pulse, the error in the charge delivered is negligible even if the pulse width of changes due to jitter. Clearly, a smaller time constant results in lower jitter sensitivity. Unfortunately, however, the peak value of the current is , thereby greatly increasing the demands made on the linearity of the loop filter.
