I. Introduction
Analog IC design automation is being dominated by optimization-based approaches using accurate electrical simulators as evaluation engines [1]–[3], however, this leads to a great overhead in terms of time consumption. Moreover, when layout effects and multiple simulations are considered to account for process variability and worst case corners [4] in the evaluation procedure, the execution time increases tenfold. A common approach to decrease the execution time of the optimizers kernels is to use parallel simulations [5], however in real world applications and environments, the software licenses for the tools are much more scarce than the available processing elements, hence the efficient use of parallelism is of the utmost importance to promote an efficient use of the available system resources.