Design automation tasks scheduling for enhanced parallel execution of a state-of-the-art layout-aware sizing approach

This paper presents an innovative methodology to efficiently schedule design automation tasks during the execution of an analog IC layout-aware sizing process. The referred synthesis process includes several sub-tasks such as DC simulation, floorplanning, placement, global routing, parasitic extraction, and circuit simulations in multiple worst case corners. The schedule of the design tasks is here optimized taking into account standard multi-core architectures, tasks dependencies, accurate time estimations for each task and a limited number of licenses for using commercial tools, e.g., number of simulator licenses. The proposed methodology, first, considers a directed acyclic graph for representing the design flow and task dependencies, then, an evolutionary kernel is used to implement a single-objective multi-constraint optimization. The efficiency and impact of the proposed approach is validated by using a state-of-the-art Analog IC design automation environment.

I. Introduction

Analog IC design automation is being dominated by optimization-based approaches using accurate electrical simulators as evaluation engines [1]–[3], however, this leads to a great overhead in terms of time consumption. Moreover, when layout effects and multiple simulations are considered to account for process variability and worst case corners [4] in the evaluation procedure, the execution time increases tenfold. A common approach to decrease the execution time of the optimizers kernels is to use parallel simulations [5], however in real world applications and environments, the software licenses for the tools are much more scarce than the available processing elements, hence the efficient use of parallelism is of the utmost importance to promote an efficient use of the available system resources.