Area efficient implementation of fast fourier transform for ASIC

The paper presents an architecture of a module for computation of a Discrete Fourier Transform with a Fast Fourier Transform algorithm. The architecture is optimized for low area implementation and is suitable for implementation in application specific integrated circuits (ASIC). Software in C++ was written for automatic FFT module generation with various parameters. The software generates fully synthesizable VHDL code and SystemVerilog testbench for verification.