Loading [MathJax]/extensions/MathMenu.js
A 12-bit 200-MS/s 3.4-mW CMOS ADC with 0.85-V supply | IEEE Conference Publication | IEEE Xplore
Scheduled Maintenance: On Monday, 30 June, IEEE Xplore will undergo scheduled maintenance from 1:00-2:00 PM ET (1800-1900 UTC).
On Tuesday, 1 July, IEEE Xplore will undergo scheduled maintenance from 1:00-5:00 PM ET (1800-2200 UTC).
During these times, there may be intermittent impact on performance. We apologize for any inconvenience.
Subscribe
ADVANCED SEARCH
Conferences >2015 Symposium on VLSI Circui...

A 12-bit 200-MS/s 3.4-mW CMOS ADC with 0.85-V supply

PDF
Joseph Palackal Mathew; Long Kong; Behzad Razavi
All Authors

Abstract:

A SAR ADC incorporates two VCOs and a TDC as a multi-bit quantizer to improve the conversion speed. Using background calibration and realized in 45-nm technology, the ADC...Show More

Metadata

Abstract:

A SAR ADC incorporates two VCOs and a TDC as a multi-bit quantizer to improve the conversion speed. Using background calibration and realized in 45-nm technology, the ADC exhibits an SNDR of 68 dB and an FOM of 8 fJ/conv. step at Nyquist.
Published in: 2015 Symposium on VLSI Circuits (VLSI Circuits)
Date of Conference: 17-19 June 2015
Date Added to IEEE Xplore: 03 September 2015
Print ISBN:978-4-86348-502-0

ISSN Information:

DOI: 10.1109/VLSIC.2015.7231330
Conference Location: Kyoto, Japan
Contents

Contact IEEE to Subscribe

References

References is not available for this document.

IEEE Account

Purchase Details

Profile Information

Need Help?

A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.
© Copyright 2025 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.