A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs | IEEE Journals & Magazine | IEEE Xplore

A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs

Publisher: IEEE

Abstract:

A feedback edge combiner is proposed for the duty-cycle corrector (DCC) of a delay locked loop (DLL) to increase the range of allowed input duty cycle. The feedback edge ...View more

Abstract:

A feedback edge combiner is proposed for the duty-cycle corrector (DCC) of a delay locked loop (DLL) to increase the range of allowed input duty cycle. The feedback edge combiner generates the rising edge of a DCC output at the rising edge of an input clock. It generates the falling edge of the DCC output at the rising edge of a feedback clock that is a half-period-delayed signal of the DCC output. A dual-delay-line digitally controlled delay line (DCDL) is used for seamless boundary switching. The chip area of the DCDL is reduced by around 46% by employing the architecture of two short coarse delay lines followed by a fine phase mixer (FPM) and a long coarse delay line in series instead of the architecture of two long coarse delay lines followed by an FPM. The measurements on the chip fabricated in the 65-nm CMOS show the allowed input duty cycle in the range from 20% to 80%; root-mean-square and peak-to-peak jitters of 2.69 and 14.0 ps, respectively, at 2 GHz and 1.2 V; and the operating frequency range from 0.12 to 2.0 GHz at 1.2 V. The measured power consumption is 3.3 mW/GHz at 1.2 V. The chip area is 0.059 mm 2 .
Published in: IEEE Transactions on Circuits and Systems II: Express Briefs ( Volume: 63, Issue: 2, February 2016)
Page(s): 141 - 145
Date of Publication: 14 August 2015

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Publisher: IEEE

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