In-memory adder functionality in 1S1R arrays

Memristive devices enable non-volatile data storage and in-memory computing capabilities. By using stateful logic approaches, hybrid CMOS nano-crossbar arrays offer additional functionalities such as arithmetic operations. To enable storage and computing on large-scale arrays, parasitic current paths within the array must be avoided. Therefore, for example, a complementary resistive switch (1CRS) or a bipolar rectifying element (‘selector’) in series to a resistive switching device (1S1R) is required at each cross-point junction to suppress low-ohmic sneak paths. In this work 1S1R arrays are considered. First, the in-memory adder concept, initially developed for CRS arrays, is adjusted for a 1S1R array. After that an optimized design is presented and verified by means of memristive simulations. Third, the energy consumption of both concepts is evaluated as a function of array size, and the delay of memristive adder designs are compared quantitatively.

I. Introduction

Redox-based resistive memories (ReRAMs) are considered as a candidate for next generation non-volatile storage solution [1], [2]. Especially highly scalable crossbar array architectures are promising candidates for the realization of ultra-dense and energy-efficient memories [3]. The key enabler for large passive crossbar arrays is the availability of a device which prevents parasitic currents [4]. In general, this could be for example a select device in series to a memristive device (1 SIR) or a complementary resistive switch (ICRS), consisting of two anti-serially connected cells [3].