A dual-edge sampling CES delay-locked loop based clock and data recovery circuits

This paper presents a dual-edge sampling clock-embedded signaling (CES) DLL based CDR. By combining the proposed dual edge sampling and half-UI embedded clock coding, the proposed method can save 4 times number of the required delay cells compared to the conventional DLL, enhancing the power efficiency and reducing silicon area. The test chip is designed in TSMC 180-nm CMOS process. The core area of the test chip is 0.519*0.137 mm² and the power efficiency of the proposed CDR is 1.43 mW/Gb/s with wide operating range of 0.5 Gb/s to 3.0 Gb/s.