Abstract:
We have designed and built a single-chip reconfigurable FFT/IFFT processor that employs a ring-structured multiprocessor architecture. Multi-level reconfigurability is re...Show MoreMetadata
Abstract:
We have designed and built a single-chip reconfigurable FFT/IFFT processor that employs a ring-structured multiprocessor architecture. Multi-level reconfigurability is realized by dynamically allocating computation resources required by specific applications. The processor IC has been fabricated in TSMC 0.25-µm CMOS. It performs 8-point to 4096-point FFT/IFFT with power-scalable features and provides useful trade-offs between algorithm flexibility, implementation complexity and energy efficiency.
Published in: 2004 12th European Signal Processing Conference
Date of Conference: 06-10 September 2004
Date Added to IEEE Xplore: 06 April 2015
Print ISBN:978-320-0001-65-7
Conference Location: Vienna, Austria