Analysis of metastability performance in digital circuits on flip-flop

Metastability events are common in digital circuits, and synchronizers are necessary to protect us from their deadly effects. Originally synchronizers were necessary when playing an asynchronous input (that is, one synchronized with the clock input so that could change exactly when the sample). Everything changes can easily be metastable. Switch its data input at the same time that the sampling edge of the clock and you get Metastability. The two signals relative duration of each cycle varies a little, and eventually leading to the metastability, close enough to each other switches. This combination of metastability with normal display devices, occur frequently. Recent semiconducting metal oxide progress (CMOS) additionally leads to unprecedented levels of integration in digital logic systems. Due to the propagation delay of the path and timing clock hold time configuration errors failure occurs in digital circuits. Depending on the application, errors are described by number of deferent terms, including “synchronization failure error” and “Metastability error”. The underlying mechanism for all of these problems is the same, and these terms “Metastability error” is the largest, because it describes the failure of the element in the circuit and not to the application. The reference signal may be either a reference voltage on the base, for example a bias voltage or a reference based on the time, as a clock signal.

I. Introduction

Metastability in electronics is the ability of a digital electronics system to persist for an unbounded time in an unstable equilibrium or metastable state. In metastable states, the circuit may be unable to settle into a stable ‘0’ or ‘1’ logic level within the time required for proper circuit operation. As a result, the circuit can act in unpredictable ways, and may lead to a system failure. It is well known fact that the synchronous systems are the data systems using a single movement of clock signal is easier to conceive (1). Any violation of synchronous design style could greatly complicate the design, rise the required analysis prohibit the use of certain aids to powerful deign, make several unnecessary testability retirements and generally increase that time of design and failure risk system.