VHDL implementation of IEEE 754 floating point unit

IEEE-754 specifies interchange and arithmetic formats and methods for binary and decimal floating-point arithmetic in computer programming world. The implementation of a floating-point systemusing this standard can be done fully in software, or in hardware, or in any combination of software and hardware. This project propose VHDL implementation of IEEE-754 Floating point unit. In proposed work the pack, unpack and rounding mode was implemented using the VHDL language and simulation was verified.