Abstract:
In this work, we propose a thermal-aware DRAM architecture and mapping for the multiple-channel three-dimensional DRAM system. A thermal-aware DRAM architecture with dual...Show MoreMetadata
Abstract:
In this work, we propose a thermal-aware DRAM architecture and mapping for the multiple-channel three-dimensional DRAM system. A thermal-aware DRAM architecture with dual control and precharge circuits (Dual-CP) is proposed to avoid the accumulated temperature by the stacking of the control and precharge circuits. A thermal-aware bank remapping (BRMAP) is proposed to avoid the active banks in the adjacent DRAM layers.
Date of Conference: 07-10 October 2014
Date Added to IEEE Xplore: 05 February 2015
Electronic ISBN:978-1-4799-5145-1
Print ISSN: 2378-8143
Department of Electrical Engineering
Innovation Center for Big Data and Digital Convergence Yuan Ze University, Jungli, Taiwan, R.O.C.
Department of Electrical Engineering
Department of Electrical Engineering
Innovation Center for Big Data and Digital Convergence Yuan Ze University, Jungli, Taiwan, R.O.C.
Department of Electrical Engineering