A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation

We propose an dynamic-voltage-scaling (DVS) non-imprinting Master-Slave SRAM with high speed erase, for low power high secured defense applications. There are three key features in the proposed design. First, the stored data is periodically toggling in the SRAM cell to prevent data imprint, hence our design is highly secured against the unauthorized attack. Once detecting the tampering attack, our SRAM can perform high speed data erase. Second, the toggling frequency in our SRAM can be scaled down to lower the toggling dynamic power dissipation without compromising the secured feature. Third, our SRAM can perform DVS from nominal voltage (V_DD =1.2V) to near-threshold voltage (V_DD =0.6V), hence further reducing the toggling leakage power. Based on the 65nm process, we simulate a DVS 1kbyte×8-bit non-imprinting SRAM (for defense application), and benchmark our design against the non-DVS counterpart. Both designs are to operate at the minimum energy point (@1MHz) via frequency scaling, but our DVS design is 84% lower idle power (for toggling) at near-threshold voltage than the non-DVS counterpart.

I Introduction

Digital SRAM is one of the most important circuit parts for a digital system since it contains of number of stored data for system operation. The stored data may contain some secret/confidential/sensitive keys for encryption and decryption of the essential information especially in defense industry. Nowadays the hackers always easily predict the SRAM information from the data imprint [1] effect on the SRAM although the power supply is off [2].