I. INTRODUCTION
Complementary metal–oxide–semiconductor (CMOS) scaling, otherwise known as Moore's law, has transformed the way we create, process, communicate, and store information in the digital age [1]– [4]. As we approach the physical limits of CMOS technology, however, it has become increasingly difficult to manage power dissipation issues [5]– [7]. The urgent need for low-power alternatives has led to a flurry of research activity on novel post-CMOS device technologies [8], [9]. Among the various post-CMOS candidates, spintronic devices have gained special attention for their potential to overcome the power and performance limitations of CMOS [10]– [12]. From a computing perspective, spintronic devices potentially have unique features—such as zero static power, instant wakeup, reduced device count, and lower switching energy—that were difficult to achieve using CMOS technology. Another intriguing feature of spintronic devices is that they could augment existing Boolean computing methods by enabling an entirely new class of architectures such as processor-in-memory, logic-in-memory, and analog/neuromorphic computing [13]– [15].