Improving calibration precision of signal-delay-based time measurement systems in FPGAs

For inherent technical reasons, most asynchronous time measurement systems, such as tapped delay lines and BOUNCE, yield superior resolutions than the synchronous counterparts. However, for high performance systems with a resolution of 10 ps or below, the calibration process is involving, tedious, and error prone. This paper shows that with the integration of another asynchronous phase shift detector, called X-ORCA, the calibration process becomes more reliable and surprisingly easy.

I. Introduction

In the field of high-precision time measurement, tapped delay lines (TDL) constitute a de facto standard [1]. Normally, a tapped delay line consists of a chain of sequentially connected flip flops (or latches). In addition, a tapped delay line features two distinct control inputs, called start signal and stop signal. The start signal is connected to the chain's first flip flop and has to travel through all the flip flops one by one. The stop signal, by contrast, is connected to the entire chain such that this signal arrives at all flip flops at the same time. Due to this internal architecture, a tapped delay line essentially counts the number of chain elements through which the start signal has rippled before the stop signal arrives. A rough sketch of a tapped delay line is presented in Fig. 1. For a more in-depth introduction into tapped delay lines, the interested reader is referred to the pertinent literature [2].