The overview of 2013 CAD contest at ICCAD

Contests and their benchmarks have become an important driving force to push our EDA domain forward in different areas lately, such as ISPD, TAU, DAC contests. The annual CAD Contest in Taiwan has been held for 13 consecutive years and has successfully boosted the EDA research momentum in Taiwan. To encourage better research development on timely and practical EDA problems across all domains, CAD Contest is internationalized since 2012 under the joint sponsorship of the IEEE CEDA and Ministry of Education (MOE) of Taiwan. 2012 CAD Contest attracted 56 teams from 7 regions, including USA, Japan, Mainland China, Hong Kong, Korea, Italy, and Taiwan. Continuing its great success in 2012, 2013 CAD contest attracts 87 teams from 9 regions, including USA, Canada, Brazil, India, Russia, Japan, Mainland China, Hong Kong and Taiwan, achieving 55% growth. Three contest problems on technology mapping, placement, and mask optimization are announced this year and run by industry experts from Cadence and IBM. Topic chair Hwei-Tseng Wang of Cadence Design Systems manages the first contest problem, concentrating on technology mapping for macro blocks. The implementation of a digital function is more flexible and powerful as technology advances. Therefore, how to fully utilize and reuse macro blocks in a highly optimized design becomes an important issue. However, it is challenging to identify the boundaries of macro blocks in such complex netlists. For the first problem, contestants are required to map and replace a given design by a set of macro blocks as much as possible. Topic chair Myung-Chul Kim of IBM manages the second problem, focusing on the placement finishing step, detailed placement and legalization. Placement, which determines locations of circuit elements, is one of the most crucial steps in the modern IC design flow. Although there are significant improvements on global placement techniques via recent placement contests, the need for high performance detailed placement continues to grow. For the second problem, contestants are required to perform local refinements on a legal design such that the total wirelength, placement/pin density are optimized. Topic chair Shayak Banerjee of IBM manages the third problem, exploring lithography mask optimization. As technology advances, the printed feature size is smaller than the wavelength of the light shining through the mask. The subwavelength gap causes unwanted shape distortions. To compensate these distortions, mask optimization is performed. For the third problem, contestants are required to find the best mask solution for a given pixelated layout. The best mask solution means least EPE violations and minimum process variations over different corners measured by a provided lithography simulation model. This session will include three presentations from the contest organizers for these contest problems and an award ceremony. Each contest organizer (topic chair) will present detailed information about the corresponding contest problem, including problem description, benchmarks, and evaluation. Along with the contest, a new set of industrial benchmarks for each contest problem will be released and facilitate scientific evaluations of related research results. We expect that the benchmark suites will further play a key driving force to push the advancement of related research. Moreover, we also expect that the participants will submit their works to the subsequent top conferences to boost related research and also extend the impacts of this contest.