12.5-Gb/s analog front-end of an optical transceiver in 0.13-μm CMOS | IEEE Conference Publication | IEEE Xplore

12.5-Gb/s analog front-end of an optical transceiver in 0.13-μm CMOS


Abstract:

In this work, a 12.5-Gb/s trans-impedance amplifier (TIA) with capacitive peaking, limiting amplifier (LA) based on the Cherry-Hooper amplifier, and high-voltage laser/mo...Show More

Abstract:

In this work, a 12.5-Gb/s trans-impedance amplifier (TIA) with capacitive peaking, limiting amplifier (LA) based on the Cherry-Hooper amplifier, and high-voltage laser/modulator driver are proposed in 0.13-μm CMOS process. The TIA and the LA operate without any inductors, and the TIA achieves a trans-impedance gain of 52.9-dBΩ and a bandwidth of 14.3GHz. The TIA and the LA use the negative Miller effect to extend the bandwidth without using any inductors. The core layout occupies an area of only 35*150 μm2. The laser/modulator driver of the transmitter drives the capacitance of the Mach-Zehnder modulator which contributes around 1.2pF. Using only thin MOS devices, the output swing of the driver exceeds 2.4V. The measurement results show the overall operating speed of 12.5-Gb/s.
Date of Conference: 19-23 May 2013
Date Added to IEEE Xplore: 01 August 2013
ISBN Information:

ISSN Information:

Conference Location: Beijing, China

I. Introduction

Recently, optical communication has been considered for short chip-chip interconnections to satisfy the demand for high speed transmissions. Circuits for using conventional copper lines incorporate many sophisticated techniques such as equalizers and multilevel signaling, to extend the limited bandwidth, which requires high power consumption and much design effort. The optical communication can resolve above problems. Without complicated circuits, very high speed communication is possible. The CMOS processes gradually reduce the cost of the optical communication while offering a bandwidth of over ten gigabits per second. With the most cost-effective CMOS process, optical transceiver front-end circuits can be designed for a speed of 12.5-Gb/s.

Contact IEEE to Subscribe

References

References is not available for this document.