Abstract:
This paper proposes a design of ultra-low-power successive approximation register (SAR) analog-to-digital converters (ADC) specially optimized for very low frequency bios...Show MoreMetadata
Abstract:
This paper proposes a design of ultra-low-power successive approximation register (SAR) analog-to-digital converters (ADC) specially optimized for very low frequency biosensor applications. Two new techniques are introduced: 1) a novel digital-to-analog converter (DAC) switching method suitable for single-ended SAR ADCs; and 2) a counter-based digital control circuitry. The DAC switching method uses VR/2 as an only reference voltage to digitize the input signals within [0, VR ], and reduces the power consumption in the DAC during digitizing by 87.5% versus the traditional one. The counter-based controller can reduce power consumption in the digital circuitry by 30%. Two prototype 8-bit SAR ADCs are designed, one in a TI 0.35-μm Bipolar-CMOS-DMOS (BCD) process and the other in a TSMC 0.18-μm CMOS process. The 0.35-μm ADC consumes 101 nW, and achieves a signal to noise and distortion ratio (SNDR) of 48.2 dB and a figure of merit (FOM) of 227 fJ/conversion-step at 2 kS/s. The 0.18-μm ADC can achieve a SNDR of 46.3 dB with only 27 nW and a FOM of 79.9 fJ/conversion-step at 2 kS/s.
Published in: IEEE Transactions on Circuits and Systems I: Regular Papers ( Volume: 60, Issue: 7, July 2013)
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