Abstract:
In this paper we present the design of an on-line adder dealing with two RBCD numbers. This basic element is intended to be be used in any on-line system in which the add...Show MoreMetadata
Abstract:
In this paper we present the design of an on-line adder dealing with two RBCD numbers. This basic element is intended to be be used in any on-line system in which the addition is involved. We obtain the on-line adder by serialization of a recent parallel RBCD adder with minimum latency.To reduce the cycle time a pipelined version is proposed. To deal with data stream the throughput has been reduced to its theoretical minimum possible value by a negligible cost hardware modification. Finally, actual implementation results for 16 digits (i.e. decimal64 format) are presented.
Published in: 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors
Date of Conference: 09-11 July 2012
Date Added to IEEE Xplore: 10 November 2012
ISBN Information:
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