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Multi-bit Sigma-Delta TDC Architecture for Digital Signal Timing Measurement | IEEE Conference Publication | IEEE Xplore

Multi-bit Sigma-Delta TDC Architecture for Digital Signal Timing Measurement


Abstract:

This paper describes the architecture (circuit design) and principles of operation of sigma-delta Sigma-Delta time-to-digital converters (TDC) for high-speed I/O interfac...Show More

Abstract:

This paper describes the architecture (circuit design) and principles of operation of sigma-delta Sigma-Delta time-to-digital converters (TDC) for high-speed I/O interface circuit test applications, they offer good accuracy with short test times. In particular, we describe multi-bit ΣΔ TDC architectures for fast testing. However, mismatches among delay cells in delay lines degrade the linearity there. Then we propose two methods to improve the overall TDC linearity: a data-weighted averaging algorithm, and a self-calibration method that measures delay values using a ring oscillator circuit. Our MATLAB and Spectre simulation results demonstrate the effectiveness of these approaches.
Date of Conference: 14-16 May 2012
Date Added to IEEE Xplore: 13 September 2012
ISBN Information:
Conference Location: Taipei
Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan
Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan
Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan
Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan
Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan
Semiconductor Technology Academic Research Center, Yokohama, Japan
Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan
Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan
Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan
Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan

Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan
Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan
Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan
Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan
Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan
Semiconductor Technology Academic Research Center, Yokohama, Japan
Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan
Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan
Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan
Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan

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