Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design

Spin-Transfer Torque Random Access Memory (STT-RAM) has been proved a promising emerging nonvolatile memory technology suitable for many applications such as cache memory of CPU. Simulation results show that the switching time of Magnetic Tunnel Junction (MTJ), which is the core element of the STT-RAM cell, varies when the temperature changes. In this paper, we study the thermal effect on switching time of STT-RAM cell, and it is showed that when temperature changes from 300K to 375K, the required write pulse period to achieve 1E-8 bit error rate (BER) increases from 10.02ns to 15.04ns under 45nm technology. When STT-RAM is used as 3-D stacked L3 cache, the required write pulse period ranges from 11.42ns to 14.68ns due to temperature variation caused by the CPU core layer. If the thermal effect is not considered, the BER of the hottest region will significantly increase to 1E-4. Based on these observations, an optimization design with Dynamic Temperature Aware Write Access is proposed, to increase the efficiency of accessing a 3-D stacked STT-RAM cache, as well as achieve the target BER. Compared to a conventional design, the proposed scheme can improve the CPU performance by 3.8% and reduce the write energy consumption of the STT-RAM cache by 4.8%.

I. Introduction

Spin-Transfer Torque Random Access Memory (STT-RAM) is one of the emerging nonvolatile memory technologies which has been intensively studied due to its fast read/write access, scalability and excellent CMOS compatibility. In STT-RAM cell, data are stored in the Magnetic Tunnel Junction (MTJ), and its resistance can be changed to High/Low state by applying write-current of different direction. The most common STT-RAM cell consists of only one transistor and one MTJ, so the density is much higher than other traditional memory technology with similar performance [1], [2].