Design of a D-PHY chip for mobile display interface supporting MIPI standard | IEEE Conference Publication | IEEE Xplore

Design of a D-PHY chip for mobile display interface supporting MIPI standard


Abstract:

This paper presents a D-PHY chip design for MIPI (Mobile Industry Processor Interface) standard. The MIPI is a flexible, source-synchronous serial interface standard conn...Show More

Abstract:

This paper presents a D-PHY chip design for MIPI (Mobile Industry Processor Interface) standard. The MIPI is a flexible, source-synchronous serial interface standard connecting a host processor to a display and camera modules as used in mobile devices. The D-PHY consists of LP (low-power) mode block, HS (high-speed) mode block and control blocks. We implemented D-PHY chip using 0.13-um CMOS process under 1.2V supply. As a result, HS mode shows 1Gbps with jitter 5% and 0.74mW power consumption.
Date of Conference: 13-16 January 2012
Date Added to IEEE Xplore: 01 March 2012
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Conference Location: Las Vegas, NV

I. INTRODUCTION

MIPI is a synchronous serial interface standard between the host processor and peripherals such as display module, camera module typically found in mobile display system. The D-PHY link supports a high-speed (HS) mode for fast data transfer and also a low-power (LP) mode for control transactions. Fig. 1 shows the MIPI D-PHY lane module that consists of a digital block for controls and an analog block for data transmission. The lane module has a transceiver portion handles differential HS functions (HS-TX, HS-RX) utilizing both interconnect wires simultaneously and single-ended LP functions (LP-TX, LP-RXs) operating on each of the interconnect wires individually. This paper presents design and simulation of low power D-PHY lane module [1] [2] [3]. Diagram of MIPI D-PHY lane modules.

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