I. INTRODUCTION
MIPI is a synchronous serial interface standard between the host processor and peripherals such as display module, camera module typically found in mobile display system. The D-PHY link supports a high-speed (HS) mode for fast data transfer and also a low-power (LP) mode for control transactions. Fig. 1 shows the MIPI D-PHY lane module that consists of a digital block for controls and an analog block for data transmission. The lane module has a transceiver portion handles differential HS functions (HS-TX, HS-RX) utilizing both interconnect wires simultaneously and single-ended LP functions (LP-TX, LP-RXs) operating on each of the interconnect wires individually. This paper presents design and simulation of low power D-PHY lane module [1] [2] [3]. Diagram of MIPI D-PHY lane modules.