I. Introduction
The fundamental task of chip testing is to determine whether a chip should be accepted or discarded, i.e, chip disposition, by measuring a set of chip surrogate metrics [1], [2]. The accepted chip is assumed to have its target metrics meeting the customer specification. If the assumption is wrong, we risk shipping “bad” chips to customers, thus increasing cost of the contracted product quality loss (PQL). Typical target metrics are operational frequency, power consumption, and robustness; while the corresponding surrogate metrics may be frequency of ring oscillators, IDDQ, and process windows.