Optimal statistical chip disposition

A chip disposition criterion is used to decide whether to accept or discard a chip during chip testing. Its quality directly impacts both yield and product quality loss (PQL). The importance becomes even more significant with the increasingly large process variation. For the first time, this paper rigorously formulates the optimal chip disposition problem, and proposes an elegant solution. We show that the optimal chip disposition criterion is different from the existing industry practice. Our solution can find the optimal disposition criterion efficiently with better yield under the same PQL constraint, or lower PQL under the same yield constraint.

I. Introduction

The fundamental task of chip testing is to determine whether a chip should be accepted or discarded, i.e, chip disposition, by measuring a set of chip surrogate metrics [1], [2]. The accepted chip is assumed to have its target metrics meeting the customer specification. If the assumption is wrong, we risk shipping “bad” chips to customers, thus increasing cost of the contracted product quality loss (PQL). Typical target metrics are operational frequency, power consumption, and robustness; while the corresponding surrogate metrics may be frequency of ring oscillators, IDDQ, and process windows.